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Vlsics Journal

India

http://airccse.org/journal/vlsi/vlsics.html

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June 2020: Top Downloaded Articles in VLSI design & Communication Systems

July 9, 2020

HARDWARE SECURITY IN CASE OF SCAN-BASED ATTACK ON CRYPTO-HARDWARE

June 26, 2020

PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS

June 17, 2020

May 2020: Top Read Articles in VLSI design & Communication Systems

June 12, 2020

COVERAGE DRIVEN FUNCTIONAL TESTING ARCHITECTURE FOR PROTOTYPING SYSTEM USING SYNTHESIZABLE ACTIVE AG

June 11, 2020

VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM

May 28, 2020

VLSI DESIGN OF AMBA BASED AHB2APB BRIDGE

May 15, 2020

IMPLEMENTATION OF LOW POWER ADIABATIC SRAM

May 6, 2020

VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITS

April 29, 2020

April 2020: Top Read Articles in VLSI design & Communication Systems!

April 22, 2020

Call for Papers - International Journal of VLSI design & Communication Systems ( VLSICS )

April 13, 2020

FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CURRENT

April 10, 2020

Call for Papers - International journal of VLSI design & Communication Systems (VLSICS)

April 6, 2020

UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE

April 3, 2020

STATIC NOISE MARGIN OPTIMIZED 11NM SHORTED-GATE AND INDEPENDENT-GATE LOW POWER 6T FINFET SRAM TOPOLO

March 23, 2020

DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR

November 5, 2019

SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SUBMICRON TECHNOLOGY

October 17, 2019

MODIFIED MICROPIPLINE ARCHITECTURE FOR SYNTHESIZABLE ASYNCHRONOUS FIR FILTER DESIGN

September 20, 2019

EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGA

September 18, 2019

DESIGN AND IMPLEMENTATION OF COMBINED PIPELINING AND PARALLEL PROCESSING ARCHITECTURE FOR FIR AND II

September 5, 2019

DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLER

August 2, 2019

CROSSTALK MINIMIZATION FOR COUPLED RLC INTERCONNECTS USING BIDIRECTIONAL BUFFER AND SHIELD INSERTION

June 26, 2019

THE DESIGN OF A LOW POWER FLOATING GATE BASED PHASE FREQUENCY DETECTOR AND CHARGE PUMP IMPLEMENTATIO

June 7, 2019

ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS FOR MICROWAVE APPLICATIO

June 3, 2019

EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATION

May 29, 2019

International Journal of VLSI design & Communication Systems ( VLSICS )

May 27, 2019

AN INVESTIGATION INTO THE RELATIONSHIPS BETWEEN LOGICAL OPERATIONS

May 27, 2019

A MULTI-OBJECTIVE PERSPECTIVE FOR OPERATOR SCHEDULING USING FINEGRAINED DVS ARCHITECTURES

May 22, 2019

OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATES

April 5, 2019

DESIGN OF A RECONFIGURABLE DSP PROCESSOR WITH BIT EFFICIENT RESIDUE NUMBER SYSTEM1

March 28, 2019

A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequen

March 25, 2019

AN EFFICIENT APPROACH FOR FOUR-LAYER CHANNEL ROUTING IN VLSI DESIGN

March 21, 2019

AN EFFICIENT APPROACH FOR FOUR-LAYER CHANNEL ROUTING IN VLSI DESIGN

March 21, 2019

DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCUITS FOR LOW POWER APPLI

March 16, 2019

International Journal of VLSI design & Communication Systems ( VLSICS )

March 15, 2019

HIGH FIN WIDTH MOSFET USING GAA STRUCTURE

March 15, 2019

DESIGN AND IMPLEMENTATION OF ANALOG MULTIPLIER WITH IMPROVED LINEARITY

March 7, 2019

QUATERNARY LOGIC AND APPLICATIONS USING MULTIPLE QUANTUM WELL BASED SWSFETS

February 19, 2019

EFFECT OF EQUAL AND MISMATCHED SIGNAL TRANSITION TIME ON POWER DISSIPATION IN GLOBAL VLSI INTERCONNE

February 5, 2019

UNIVERSAL ROTATE INVERT BUS ENCODING FOR LOW POWER VLSI

February 1, 2019

DELAY ERROR WITH META-STABILITY DETECTION AND CORRECTION USING CMOS TRANSMISSION LOGIC

January 4, 2019

Design and Implementation A different Architectures of mixcolumn in FPGA

January 3, 2019

DEADLOCK RECOVERY TECHNIQUE IN BUS ENHANCED NOC ARCHITECTURE

December 28, 2018

A REVIEW OF THE 0.09 µm STANDARD FULL ADDERS

December 22, 2018

EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND

December 19, 2018

DESIGN AND PERFORMANCE ANALYSIS OF ULTRA LOW POWER 6T SRAM USING ADIABATIC TECHNIQUE

December 13, 2018

Design of Efficient Adder Circuits Using PROPOSED PARITY PRESERVING GATE (PPPG)

December 11, 2018

PERFORMANCE EVALUATION OF CDMAROUTER FOR NETWORK - ON - CHIP

December 7, 2018