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STATIC NOISE MARGIN OPTIMIZED 11NM SHORTED-GATE AND INDEPENDENT-GATE LOW POWER 6T FINFET SRAM TOPOLO

May 31, 2023

AN EFFICIENT SEGMENTED RANDOM ACCESS SCANARCHITECTURE WITH TEST COMPRESSION

May 17, 2023

DUTY CYCLE CORRECTOR USING PULSE WIDTH MODULATION

May 3, 2023

DESIGN AND IMPLEMENTATION OF COMBINED PIPELINING AND PARALLEL PROCESSING ARCHITECTURE FOR FIR AND II

April 26, 2023

DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSOR

April 19, 2023

CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS OF REGULAR THREE-DIMEN

March 29, 2023

APPROXIMATE ARITHMETIC CIRCUIT DESIGN FOR ERROR RESILIENT APPLICATIONS

January 18, 2023

CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS OF REGULAR THREE-DIMEN

October 7, 2022

CONCURRENT TERNARY GALOIS-BASED COMPUTATION USING NANO-APEX MULTIPLEXING NIBS OF REGULAR THREE-DIMEN

September 28, 2022

AREA, DELAY AND POWER ANALYSIS OF BUILT IN SELF REPAIR USING 2-D REDUNDANCY

August 18, 2022

Design and Implementation of FPGA Based Signal Processing Card

June 30, 2022

June 2022: Top 10 Read Articles in VLSI design & Communication Systems

June 23, 2022

Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA

June 16, 2022

Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip

June 9, 2022

Pipelined Architecture of 2D-DCT, Quantization& ZigZag Process for JPEG Image Compression Using VHDL

June 2, 2022

May 2022: Top Read Articles in VLSI design & Communication Systems

May 26, 2022

Sub Ten Micron Channel Devices Achieved by Vertical Organic Thin Film Transistor

May 19, 2022

Power Comparison of CMOS and Adiabatic Full Adder Circuits

May 12, 2022

Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power Applications

May 5, 2022

April 2022: Top Read Articles in VLSI design & Communication Systems

April 28, 2022

FPGA Implementation of Soft Output Viterbi Algorithm Using Memoryless Hybrid Register ExchangeMethod

April 21, 2022

A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

April 7, 2022

Test Generation for Analog and Mixed-Signal Circuits Using Hybrid System Models

March 31, 2022

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

March 24, 2022

Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization

March 17, 2022

Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology

March 10, 2022

International Journal of VLSI design & Communication Systems (VLSICS), H index - Profile

February 24, 2022

A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs

February 10, 2022

Call for Papers (February Issue) - International Journal of VLSI design & Communication Systems

February 8, 2022

Using CMOS Sub-Micron Technology VLSI Implementation of Low Power High Speed SRAM Cell and DRAM Cell

February 3, 2022

Low Power Low Voltage Bulk Driven Balanced OTA

January 27, 2022

Design and ASIC Implemenatation of DUC/DDC for Communication Systems

January 20, 2022

An Efficient FPGA Implemenation of MRI Image Filtering and Tumour Characterization Using XILINX Syst

January 13, 2022

VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

December 30, 2021

December 2021: Top Read Articles in VLSI design & Communication Systems

December 28, 2021

A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Physical Design Implementat

December 23, 2021

Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

December 9, 2021

Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate

December 2, 2021

Call for Papers - International Journal of VLSI design & Communication Systems (VLSICS)

November 30, 2021

Design of Reversible Sequential Circuit Using Reversible Logic Synthesis

November 25, 2021

November 2021: Top Read Articles in VLSI design & Communication Systems

November 23, 2021

FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC

November 18, 2021

A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates

November 11, 2021

Call for Papers (Dec Issue) - International Journal of VLSI design & Communication Systems (VLSICS)

November 9, 2021

A New Full Adder Cell for Molecular Electronics

October 28, 2021

Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Universal Logic Gates

October 21, 2021

Arithmetic Operations in Multi-Valued Logic

October 7, 2021

QoS Based Capacity Enhancement for WCDMA Network with Coding Scheme

September 30, 2021