ABSTRACTThe purpose of the present paper is to investigate the composition of the coating formed on the plasma reactor walls after an industrial process which is divided into two steps, where the chemistries used are CF4/CH2F2followed by... more
ABSTRACTThe purpose of the present paper is to investigate the composition of the coating formed on the plasma reactor walls after an industrial process which is divided into two steps, where the chemistries used are CF4/CH2F2followed by HBr/O2. Since Fluorine traces have been detected through the plasma and over the wafer even during the second chemistry, investigations of the Br-F chemistry duality for a new silicon etching process have been performed in order to see the reactions which are taking place inside of the reactor. The understanding of these formations is really important to avoid process instabilities and get better performance of the transistors. The coating on the walls after the process and after the cleaning between wafers has been characterized in order to figure out the level of F traces after each step and to understand the reminiscence of this element over time. This study is the starting point to propose a modification on the Waferless AutoClean (WAC) used now...
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The semiconductor manufacturing industry has a large-volume multistage manufacturing system. To insure the high stability and the production yield on-line a reliable wafer monitoring is required. The approach, called Virtual Metrology... more
The semiconductor manufacturing industry has a large-volume multistage manufacturing system. To insure the high stability and the production yield on-line a reliable wafer monitoring is required. The approach, called Virtual Metrology (VM) is defined as the prediction of metrology variables (either measurable or non measurable) using process and wafer state information. It consists in the definition and the application of some predictive and corrective models for metrology outputs (physical measurements) in function of the previous metrology outputs and of the equipment parameters of current and previous steps of fabrication. The goals of this paper are to present a methodology for VM module for individual process applications in semiconductor manufacturing and to present a case study based on industrial data.
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ABSTRACT With geometries scaling down and the considerable multiplication of process recipes used in production for the same furnace, it becomes more and more difficult and hard to tune all process recipes correctly to achieve target... more
ABSTRACT With geometries scaling down and the considerable multiplication of process recipes used in production for the same furnace, it becomes more and more difficult and hard to tune all process recipes correctly to achieve target deposition thickness performances. In this paper diffusion furnace recipes control using run to run (R2R) will be presented and described. The goal is to be able to control all furnace recipes using transfer models and corrective factors.
ABSTRACT We propose a method to model the wet etch process within the Shallow Trench Isolation (STI) module in the CMOS technology. To model a process is the first step in the design of a run to run system, in order to reduce for example... more
ABSTRACT We propose a method to model the wet etch process within the Shallow Trench Isolation (STI) module in the CMOS technology. To model a process is the first step in the design of a run to run system, in order to reduce for example the lot to lot variability (a lot equals 25 wafers). The developed predictive model is based on a Design Of Experiments (DOE).
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Tool condition evaluation and prognosis has been an arduous challenge in modern semiconductor manufacturing environment, especially for the foundry and analog companies with high product-mix and complicated technology nodes. More and more... more
Tool condition evaluation and prognosis has been an arduous challenge in modern semiconductor manufacturing environment, especially for the foundry and analog companies with high product-mix and complicated technology nodes. More and more embedded and external sensors are installed to capture the genuine tool status for tool fault identification and, thus, tool condition analysis based on real-time equipment data becomes promising
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... Agnes Roussy, Christelle Kernaflen Department of Manufacturing Science and Logistics Ecole Nationale Supérieure des Mines de SaintEtienne Gardanne, France ... gleisp ach @ au striamicrosvstems.com Hervé Gris, J érome Besnard PDF... more
... Agnes Roussy, Christelle Kernaflen Department of Manufacturing Science and Logistics Ecole Nationale Supérieure des Mines de SaintEtienne Gardanne, France ... gleisp ach @ au striamicrosvstems.com Hervé Gris, J érome Besnard PDF Solutions Montpellier, France herve. ...
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ABSTRACT Targeting the physical gate critical dimension (CD) greatly impacts device performance. Unfortunately, advanced products within the CMOS logic 0.13 μm technology suffer from a large gate CD lot-to-lot variation, thereby causing... more
ABSTRACT Targeting the physical gate critical dimension (CD) greatly impacts device performance. Unfortunately, advanced products within the CMOS logic 0.13 μm technology suffer from a large gate CD lot-to-lot variation, thereby causing an important device parametric characteristics variability. A novel technique is to develop a feedforward controller, which corrects for gate CD deviation by tuning the pocket implant dose. In order to enhance the controller robustness, a new scatterometry grating has been considered. The FFE-PI2 control system is simulated and then implemented in a 8" semiconductor device manufacture. Results indicate a 40% decrease in lot-to-lot variation of transistor performance.
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A new NbN multilayer technology has been developed on 3 inch diameter R-plane sapphire substrates, for combining on-chip fast RSFQ circuits with GHz bandwidth optical links, The circuits take advantage of two high quality (110) NbN layers... more
A new NbN multilayer technology has been developed on 3 inch diameter R-plane sapphire substrates, for combining on-chip fast RSFQ circuits with GHz bandwidth optical links, The circuits take advantage of two high quality (110) NbN layers sputtered epitaxially on sapphire at 600°C and selectively patterned: a 400 nm thick layer (λ L~250 nm at 6 K) acts for the
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A frequency dependent inductance estimation has been carried out for Rapid-Single-Flux Quantum (RSFQ) applications in NbN multilayer technology up to frequencies above the NbN gap frequency. For this purpose an extension of the fullwave... more
A frequency dependent inductance estimation has been carried out for Rapid-Single-Flux Quantum (RSFQ) applications in NbN multilayer technology up to frequencies above the NbN gap frequency. For this purpose an extension of the fullwave modified transverse resonance method (MTRM) has been used, in which each superconducting layer is characterized by its complex conductivity according to the BCS derived model of Mattis and Bardeen. Our estimation shows significant influence of the gap frequency on the NbN multilayer structure inductance at high frequencies.