VLSI

V. SUMMARY We have given parallel algorithms for recognizing and parsing context-free languages on a hypercube of p PE's, 1 5 p 5 n. The algorithms are both time-wise and space-wise optimal with respect to the most efficient sequential algorithm. The recognition algorithms were ...

Less than 116 ps overall clock skew has been achieved across the 15.02 mm/spl times/15.03 mm die by balanced clock path routing and differential clock signal distribution in the global clock tree of 300 MHz 128-bit 2-way superscalar microprocessor. The shared clock wire configuration and clock buffer layout patterns over the whole die enhance the clock skew insensitivity to process

The scaled Chinese Remainder Theorem (CRT) is a very useful tool for the simplification of RNS to binary converters. The main drawback of this methodology is related to the use of large look-up tables that store the correspondence among the modular numbers and the corresponding scaled terms of the CRT. This fact limits the maximum speed allowed by this approach. In this paper a new method for the computation of the scaled factors is presented. It allows the computation of the scaled CRT output by using very small look-up tables implemented by conventional logic and simple and fast structures, that work in parallel. The only assumption made in order to develop the new algorithm is that the moduli must be odd

Capacitively-driven on-chip wires reduce both latency and energy compared to repeaters. A series coupling capacitance offers preemphasis to lower wire delay, reduces the driven load, and lowers the wire voltage swing without a second power supply. A 0.18mum CMOS testchip shows 10.5times energy savings at a 50mV swing compared to full-swing repeated wires, and a 3times gain in wire bandwidth

The present paper explores and analyses the performance of Carbon Nano Tube Field Effect Transistor (CNTFET) technology in analog domain through its application as a basic current mirror. 32nm channel length-single walled-one tube CNTFET technology has been assessed and compared with 45nm, 32nm and 22nm NMOS technologies through HSPICE simulations of current mirror circuitry. Different methods of comparison like current error, input-output resistances, AC small signal and transient analysis have been employed which highlight the benefits of CNTFET over NMOS technology and its potential to be used for analog VLSI.

Emerging semiconductor VLSI requires improved device density on a single chip solution that many parameters are becoming vital concern for cost reduction by lowering the chip area, lowering power dissipation, reducing operating voltage, increasing speed etc. A previously designed precision sensor application mirror-amplifier was considered for optimizing in chip area consumption and improves sensing to make it ultra-precise, also this work has reduced the IC to a subcompact die sizes. MAGIC is used as two-dimensional CAD layout tool. Also PSPICE is used for electrical simulation purposes employed by extraction tool. Feature size is taken from mSCN3M_SUBM.30 process for 0.6µm layout and 0.5µm enhanced fabrication process. The improved design has area of 101λX48λ (minimized from 126λX59λ) or 30.3µmX15µm (minimized from 37.8µmX17.7µm) in 0.6µm CMOS design process. For multi-die placement, two sets of chip are designed those are placed on the four sub-dies in a single MOSIS tinychip die. For one set of chip coincidence detector is designed to make the mirror-amplifier ultra precise, buffer stage is designed for another set of chip to drive large load. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

This paper presents a comparative study of Complementary MOSFET (CMOS) full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. Full adder circuit is an essential component for designing of various digital systems. It is used for different applications such as Digital signal processor, microcontroller, microprocessor and data processing units (DSP). In most of these systems the adder lies in the critical path that determines the overall speed of the system. Full adder is mainly used in VLSI devices like microprocessor for computational purposes. The proposed full adder cell has low power consumption, better area efficiency. Recently, there have been massive research interests in this area due to the growing need for low-power and highperformance computing systems. Our aim is to design and compare the full adder circuit in various technologies and compare their power capacity. By using the hybrid structure of NMOS and PMOS, we have implemented the circuit of full adder.

This paper presents a scalable and systolic Montgomery's algorithm in GF(2m) using the Hankel matrix-vector representation. The hardware architectures derived from this algorithm represents low-complexity bit-parallel systolic multipliers with trinomials. The results reveal that our proposed multiplier saves approximately 36% space complexity as compared to an existing systolic Montgomery multiplier for trinomials. Moreover, the proposed architectures have the features of regularity, modularity, and local interconnect ability. Accordingly, they are well suited for VLSI implementation

With the advancement in the field of electronics at an incredible pace, the power efficient and high-speed VLSI designs are gaining more popularity and are highly in demand. The decrease in battery weight, size and increase in the lifetime are the key factors for portable equipments. Most of the reported multipliers have very poor performance and/or become non-functional in case of low-voltage, low-power environment. This paper describes various applications of analog multiplier such as frequency doubler, modulator, demodulator etc. All the simulation work has been done on Tanner EDA tool at 45nm technology.

In this paper, we present a basis for treating, evaluating and measuring knowledge as an energy acquired by knowledge centric objects in society. The energy level acquired is indicated as their knowledge potential or KnP. Some objects get more charged in the knowledge domain and exhibit a longer and/or more intense energy trail. The Rate of knowledge acquisition, intellectual caliber and need intensity driving to acquire knowledge all play a role in the knowledge energy (Kenergy) thus acquired. Bounded by established principles of measurement, units, quantification and equations for dealing with knowledge, it becomes amenable to its own (knowledge) science with laws derived from the many disciplines and their own distinctive principles. We fall back on equations from thermodynamics, electrical engineering, fluid mechanics and transmission theory to quantify the flow-properties of knowledge. Though not completely precise and accurate at this stage of development in the science of kno...

Crosstalk noise is a crucial factor affecting chip performance in deep submicron technologies. Among all possible crosstalk noise sources, clock is the most common aggressor as well as victim. Crosstalk on clock nets can increase clock jitter, which may degrade significantly the system performance. It is therefore imperative to design clock buffers to reduce the coupling effects. In this paper, we address the crosstalk effect on clock networks. We propose an algorithm to size clock buffers for given buffered clock trees such that the induced clock jitter is minimized. Our experimental results show a significant reduction of clock jitter by sizing the clock buffers without increasing the total area of buffer.

Abstract: In thispaper, the notion of equivalent embedding of rectangular duals (jloorplans) is introduced which leads to a new concept of canonical embedding of a rectangular dual; this isajloorplan corresponding to agivenneighbor-hood graph such that the number of ...