The aim of this work is to study how the performance of nanowire tunnel field effect transistors (TFETs) is influenced by temperature variation. First of all, simulated energy band diagrams were presented to justify its fundamental... more
The aim of this work is to study how the performance of nanowire tunnel field effect transistors (TFETs) is influenced by temperature variation. First of all, simulated energy band diagrams were presented to justify its fundamental working principle and this analysis was compared to experimental data obtained for temperature ranging from 300 to 420 K. This methodology was performed for different nanowire diameters and bias conditions, leading to a deep investigation of parameters such as the ratio of on-state and off-state current (ION/IOFF) and the subthreshold slope (S). Three different transport mechanisms (band-to-band tunneling, Shockley-Read-Hall generation/recombination and trap-assisted tunneling) were highlighted to explain the temperature influence on the drain current. As the final step, subthreshold slope values for each configuration were compared to the room temperature. Therefore, it was observed that larger nanowire diameters and lower temperatures tended to increase...
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This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which... more
This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) prese...
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In this work a discussion on the estimated volume trap densities (NT) compared to surface traps densities (Neff) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise... more
In this work a discussion on the estimated volume trap densities (NT) compared to surface traps densities (Neff) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise spectroscopy is made. The investigated devices present a fin width of 10 nm, a fin height of 10 nm and four fins in parallel, leading to an equivalent channel width of 120 nm. The equivalent oxide thickness (EOT) is 5.6 nm. More details on the device fabrication and experimental setup may be found in [1,2]. The noise spectra and the estimated surface traps densities are provided in [3]. In this work, focus is only on the identified T4 trap, for which using the linear dependence that should exist between A0i and t0i related to the same trap, without any other assumption, a surface trap density of 2.8∙1012cm-2 is obtained [3]. It should be noted that from the 1/f flat-band noise level an interface trap density value of about 1.9∙1018 eV-1cm-3 is obtained at 300 ...
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This paper describes a detailed experimental comparative study between nMuGFETs implemented with tensile and compressive stresses when submitted to X-ray radiation, taking into account different doses and different channel widths and... more
This paper describes a detailed experimental comparative study between nMuGFETs implemented with tensile and compressive stresses when submitted to X-ray radiation, taking into account different doses and different channel widths and lengths of the devices. The experimental results show that the intrinsic voltage gain and the unit voltage gain frequency for tensile stressed devices always present a higher immunity to the X-ray radiation (up to 50 Mrad).
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Research Interests: Engineering, Computer Science, IEEE, Data retention, Scaling, and 3 moreScalability, DRAM, and Retention Time
Although scaled down technologies may suffer from statistical parameter fluctuations caused by process variability, they are potentially radiation hard from a total-dose perspective. Therefore, the proton radiation hardness of a... more
Although scaled down technologies may suffer from statistical parameter fluctuations caused by process variability, they are potentially radiation hard from a total-dose perspective. Therefore, the proton radiation hardness of a high-κ/metal gate 45 nm CMOS technology is studied using wafer level testing on 300 mm wafers. Attention is given to the correlation between pre- and post-radiation parameter variations. It is demonstrated that both the pre-irradiation process variability and the radiation-induced variability of the parameters have to be taken into account. For devices with a capping layer, the type of dielectric layer has an impact on the radiation-induced trapping mechanisms.
Research Interests: Materials Science, Radiation, Optoelectronics, Cmos, Radiation Hardening, and 2 moreIrradiation and Wafer(Irradiation and Wafer)
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ABSTRACT This paper aims to analyze the band gap and the pulsed back gate bias influence on the retention time of an UTBOX SOI applied as a 1T-DRAM memory cell. This parameter is increased for higher band gap and constant whatever the... more
ABSTRACT This paper aims to analyze the band gap and the pulsed back gate bias influence on the retention time of an UTBOX SOI applied as a 1T-DRAM memory cell. This parameter is increased for higher band gap and constant whatever the pulsed back gate level during the write state. No significant difference on the retention time was observed when comparing the pulsed and constant back gate bias.
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In this work the gate induced floating body effect (GIFBE) was analysed in FinFET devices in function of the substrate bias. This analysis was performed in strained and unstrained devices that were fabricated with and without selective... more
In this work the gate induced floating body effect (GIFBE) was analysed in FinFET devices in function of the substrate bias. This analysis was performed in strained and unstrained devices that were fabricated with and without selective epitaxial grow (SEG). For all evaluated devices, this analysis results in a "U" shape behavior of GIFBE onset. Strained devices present earlier GIFBE due to the band gap variation as well as the presence of SEG structure.
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The low-frequency noise of shallow germanium p+-n junctions is studied, for diodes with or without a nickel-germanide Ohmic contact. It is shown that the application of NiGe not only reduces the series resistance, resulting in a higher... more
The low-frequency noise of shallow germanium p+-n junctions is studied, for diodes with or without a nickel-germanide Ohmic contact. It is shown that the application of NiGe not only reduces the series resistance, resulting in a higher forward current, but also results in a lower 1∕f noise at forward bias. From the observed geometry dependence, it is concluded that germanidation suppresses the 1∕f noise generated in the series resistance, leaving surface-state-assisted generation-recombination at the junction perimeter as the dominant flicker noise source.
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In this work, the formation of donors in n-type high resistivity magnetic Czochralski-grown silicon wafers, directly exposed to a hydrogen plasma, is investigated by a combination of capacitance-voltage (C-V) and deep level transient... more
In this work, the formation of donors in n-type high resistivity magnetic Czochralski-grown silicon wafers, directly exposed to a hydrogen plasma, is investigated by a combination of capacitance-voltage (C-V) and deep level transient spectroscopy (DLTS) measurements. C-V analysis demonstrates diffusionlike concentration profiles close to the surface, pointing to the formation of hydrogen-related shallow donors in silicon during the hydrogenation. In addition, oxygen thermal donors are created during a subsequent annealing (20min) performed at 350–450°C, as demonstrated by DLTS. It is shown that the hydrogen-related shallow donors are the dominant donors in as-hydrogenated samples, while hydrogen acts as a catalyst during the formation of oxygen thermal donors in the temperature range of 350–450°C. It is finally shown that the formation of both kinds of donors is Fermi-level dependent.
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The impact of high-temperature neutron, electron, and γ-irradiations on the dark current of silicon p–i–n junctions is described in terms of a damage coefficient KI. It is shown that this KI is thermally activated and reduces for... more
The impact of high-temperature neutron, electron, and γ-irradiations on the dark current of silicon p–i–n junctions is described in terms of a damage coefficient KI. It is shown that this KI is thermally activated and reduces for increasing irradiation temperature. The same activation energy is retrieved when studying the isochronal annealing behavior of a set of room-temperature irradiated diodes. This leads to a simple method to predict the high-temperature KI from only room-temperature irradiations combined with a thermal annealing study.
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In this work the influence of the substrate rotation on the analog performance of strained SOI MuGFETs is presented. Measurements performed in fabricated devices show a degradation of the maximum transconductance at both linear and... more
In this work the influence of the substrate rotation on the analog performance of strained SOI MuGFETs is presented. Measurements performed in fabricated devices show a degradation of the maximum transconductance at both linear and saturation regime. The substrate rotation has no influence on the output conductance. The intrinsic voltage gain and the unit gain frequency were extracted and presented a reduction promoted by substrate rotation, being more evident for a narrow fin.
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This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the... more
This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.
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One of the main challenging issues for germanium (Ge) devices is the gate stack engineering which determines the interface state density (NIT) and the associated channel/oxide interface quality. This paper shows how this issue can play a... more
One of the main challenging issues for germanium (Ge) devices is the gate stack engineering which determines the interface state density (NIT) and the associated channel/oxide interface quality. This paper shows how this issue can play a role in p-channel Ge MOSFETs considering both the operation mode, i.e., comparing conventional, dynamic threshold voltage (DT, where VBS = VGS) and enhanced dynamic threshold voltage (eDT, where VBS=k*VGS) modes, and the main analog parameters like the Early voltage (VEA) and intrinsic voltage gain (AV). Moreover, the impact of different HfO2/Al2O3 gate stack thicknesses is under evaluation. Although the thinnest Al2O3 layer degrades all evaluated parameters, specifically: lower VEA and AV, higher drain current hysteresis and subthreshold swing (SS) due to the higher NIT, the dynamic threshold voltage showed to be an effective mode to strongly minimize the hysteresis effects and improves up to 60% in eDT (k = 2) mode compared to the conventional mod...
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This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures (from room temperature up to... more
This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures (from room temperature up to 573K). The study takes into account temperature dependent model parameters such as threshold voltage and channel mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplifications used for the VZTC model as a function of temperature in the linear and the saturation regime.
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In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel... more
In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion.
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In this paper, the impact of the thickness of the highAl2O3 capping layer on the low-frequency noise performance of nMOSFETs with 8 nm SiO2 and TiN gate metal has been investigated. It is shown that the predominant 1/f noise is governed... more
In this paper, the impact of the thickness of the highAl2O3 capping layer on the low-frequency noise performance of nMOSFETs with 8 nm SiO2 and TiN gate metal has been investigated. It is shown that the predominant 1/f noise is governed by the number fluctuations mechanism. The presence of an Al2O3 cap increases the noise Power Spectral Density and, hence, the oxide trap density. Keywords— Low-frequency noise, Al2O3 capping layer, Oxide trap density, TiN gate
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This paper reports an analysis of radiation effects on triple gate SOI tunnel FETs from a total ionizing dose point of view, based on measurements and TCAD simulations. Devices with different dimensions were exposed to a dose of... more
This paper reports an analysis of radiation effects on triple gate SOI tunnel FETs from a total ionizing dose point of view, based on measurements and TCAD simulations. Devices with different dimensions were exposed to a dose of 1 Mrad(Si) generated by a 600 keV proton radiation source. It was possible to notice a drain current decrease for irradiated devices that reduces with increasing channel length and gate bias. To explain this behavior, the influence of positive charges at front and back interfaces generated by the cumulative exposure to radiation was analyzed, as well as devices’ internal characteristics for such operation conditions. This analysis is based on the competition between a high channel resistance present in longer devices and the TFET drain current reduction due to the irradiation.
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Ge pFinFETs, fabricated either with an STI last process on a Ge-on-Si virtual substrates or a SiGe strain-relaxed buffer, have been systematically evaluated at temperatures from 200 K down to 77 K. In the first cases, the Ge channel is... more
Ge pFinFETs, fabricated either with an STI last process on a Ge-on-Si virtual substrates or a SiGe strain-relaxed buffer, have been systematically evaluated at temperatures from 200 K down to 77 K. In the first cases, the Ge channel is relaxed, while in the second case, compressively strained fins have been obtained. Cryogenic testing shows to be an important tool for evaluating the static device performance parameters and it helps to resolve the impact of strain on the drain current. Apart from that, the off-state leakage in the subthreshold region can be evaluated as a function of temperature, showing that besides thermal Shockley-Read-Hall generation, other field-assisted mechanisms play a role.
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The paper briefly reviews some of the present-day state-of-the art III-V devices processed on a Si platform reported in the literature, before addressing defect engineering aspects for III-V processing on a Si substrate from both a... more
The paper briefly reviews some of the present-day state-of-the art III-V devices processed on a Si platform reported in the literature, before addressing defect engineering aspects for III-V processing on a Si substrate from both a structural and electrical performance perspective. The identification of the extended defects will be illustrated by some case studies based on leakage current and lifetime investigations, Deep Level Transient Spectroscopy (DLTS) analysis and low frequency noise spectroscopy. Information on the basic defect parameters can be used as input for TCAD simulation of the electrical device performance, enabling a further optimization of the materials’ growth and process conditions.
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The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript.... more
The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript. This study aims to explain the fin width dependence of the threshold voltage from experimental data and evaluates the ground plane doping concentration and its depth influence on relaxed p-type channel germanium FinFET parameters, as threshold voltage, transconductance and subthreshold swing, through Technology Computer-Aided Design (TCAD) numerical simulations. The threshold voltage variation reaches up to 80 mV from the narrowest device to the widest one, considering the studied range of ground plane doping concentration. Concerning the subthreshold swing parameter, neither the GP doping concentration, nor its depth play a significant role since the electrostatic coupling is predominant.