alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation
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Verilog Ethernet components for FPGA implementation
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
HDL libraries and projects
The USRP™ Hardware Driver Repository
PicoRV32 - A Size-Optimized RISC-V CPU
Verilog Configurable Cache