User:1sfoerster/enes245/fall2014/FIR FPGA SDR filter: Difference between revisions
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k k=0 |
k k=0 |
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Based on this equation, we will need the following modules: |
Based on this equation, we will need the following modules: |
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- Multiplier |
-- Multiplier |
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- Adders |
-- Adders |
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-Memories: to store the filter coefficients,to store past sample values. |
--Memories: to store the filter coefficients,to store past sample values. |
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-Control block : to coordinate the multiplier. |
--Control block : to coordinate the multiplier. |
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- Address generator: to get the appropriate coefficients and delayed sample values. |
- -Address generator: to get the appropriate coefficients and delayed sample values. |
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First, I will Matlab( HDL suite) to examine the frequency response of the filtering. |
First, I will Matlab( HDL suite) to examine the frequency response of the filtering. |
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Next , I will write theVHDL code performing the desired filtering. |
Next , I will write theVHDL code performing the desired filtering. |
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Finally I will test the VHDL code by comparing its outputs with the filter created in Matlab. |
Finally I will test the VHDL code by comparing its outputs with the filter created in Matlab. |
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Revision as of 11:48, 12 May 2015
Problem
We are now living in an age of Information Technology; most of information technology is based on DSP( digital signal processing). Telecommunication, speech processing, consumer electronics, image processing and biomedical systems are some applications of DSP. Filtering is the most common part of DSP and it is used in all the previously mentioned applications. So what are filters? filters are mainly used in signal processing to remove unwanted frequencies from an incoming signal. FIR's and IIR's are described as the two filter types found in Software Defined Radio. The goal is to build a FIR in a papilio to and figure out how they work. Ultimately the goal is to connect it to open source SDR software running in a computer. FIR's and IIR's are described as the two filter types found in Software Defined Radio. The goal is to build a FIR in a papilio to and figure out how they work. Ultimately the goal is to connect it to open source SDR software running in a computer.
Conceive
- Read this FIR filter basics.
- Read this wikipedia FIR entry
- Read this paper up to figure 2.
Design
Repeat this project
I will try here to design a simple FIR FPGA SSR filter; this filter will be generic and very flexible. In general, the equation to generate a simple DSP filter is given by: y[n]=∑b x[n−k] k k=0
Based on this equation, we will need the following modules:
-- Multiplier -- Adders --Memories: to store the filter coefficients,to store past sample values. --Control block : to coordinate the multiplier. - -Address generator: to get the appropriate coefficients and delayed sample values.
First, I will Matlab( HDL suite) to examine the frequency response of the filtering.
Next , I will write theVHDL code performing the desired filtering.
Finally I will test the VHDL code by comparing its outputs with the filter created in Matlab.
Implement
Demo
Next Steps
Write summary of the conceive reading above.
Looks like the following MathWorks tool boxes may help push this project forward. In any case they need to be part of the SDR software tools learned:
- The DSP System Toolbox is included in the student Simulink tool box
- Signal processing tool box which contains the FDAtool
- Filter Design HDL Coder