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In memory addressing for Intel x86 computer architectures, segment descriptors are a part of the segmentation unit, used for translating a logical address to a linear address. Segment descriptors describe the memory segment referred to in the logical address.^[1] The segment descriptor (8 bytes long in 80286 and later) contains the following fields:^[2]

A segment base address
The segment limit which specifies the segment size
Access rights byte containing the protection mechanism information
Control bits

Structure[edit]

The x86 and x86-64 segment descriptor has the following form:^[3]

Where the fields stand for:

Base Address: Starting memory address of the segment. Its length is 32 bits and it is created from the lower part bits 16 to 31, and the upper part bits 0 to 7, followed by bits 24 to 31.
Segment Limit: Its length is 20 bits and is created from the lower part bits 0 to 15 and the upper part bits 16 to 19. It defines the address of the last accessible data. The length is one more than the value stored here. How exactly this should be interpreted depends on the Granularity bit of the segment descriptor.
G=Granularity: If clear, the limit is in units of bytes, with a maximum of 2²⁰ bytes. If set, the limit is in units of 4096-byte pages, for a maximum of 2³² bytes.
D/B: D = Default operand size : If clear, this is a 16-bit code segment; if set, this is a 32-bit segment.; B = Big: If set, the maximum offset size for a data segment is increased to 32-bit 0xffffffff. Otherwise it's the 16-bit max 0x0000ffff. Essentially the same meaning as "D".
L=Long: If set, this is a 64-bit segment (and D must be zero), and code in this segment uses the 64-bit instruction encoding. "L" cannot be set at the same time as "D" aka "B". (Bit 21 in the image)
AVL=Available: For software use, not used by hardware (Bit 20 in the image with the label A)
P=Present: If clear, a "segment not present" exception is generated on any reference to this segment
DPL=Descriptor privilege level: Privilege level (ring) required to access this descriptor
S=System Segment: If clear, this is system segment, if 1, this is Code/Data segment.
Type: If bit 11 set, this is a code segment descriptor. If clear, this is a data/stack segment descriptor, which has "D" replaced by "B", "C" replaced by "E" and "R" replaced by "W". This is in fact a special case of the 2-bit type field, where the preceding bit 12 cleared as "0" refers to more internal system descriptors, for LDT, LSS, and gates.
C=Conforming: Code in this segment may be called from less-privileged levels.
E=Expand-Down: If clear, the segment expands from base address up to base+limit. If set, it expands from maximum offset down to limit, a behavior usually used for stacks.
R=Readable: If clear, the segment may be executed but not read from.
W=Writable: If clear, the data segment may be read but not written to.
A=Accessed: This bit is set to 1 by hardware when the segment is accessed, and cleared by software.

References[edit]

^ Bovet, D.P., & Cesati, M. (2000). Understanding the Linux Kernel (First Edition). O'Reilly & Associates, Inc.
^ Tabak, Daniel (1995). Advanced Microprocessors. Mcgraw Hill Publishers. p. 149. ISBN 9780070628434.
^ AMD64 Architecture Programmer's Manual Volume 2: System Programming (PDF) (Technical report). 2013. p. 80. Archived from the original (PDF) on 2018-02-18.

Tabak, Daniel (1991). Advanced Microprocessors. McGraw Hill and Co. ISBN 9780070628076.
Hall, Douglas. Microprocessors and Interfacing. McGraw Hill Publications.

External links[edit]

Intel 80386 Reference Programmer's Manual - Segment Translation

This computer hardware article is a stub. You can help Wikipedia by expanding it.

[1] Bovet, D.P., & Cesati, M. (2000). Understanding the Linux Kernel (First Edition). O'Reilly & Associates, Inc.

[2] Tabak, Daniel (1995). Advanced Microprocessors. Mcgraw Hill Publishers. p. 149. ISBN 9780070628434.

[3] AMD64 Architecture Programmer's Manual Volume 2: System Programming (PDF) (Technical report). 2013. p. 80. Archived from the original (PDF) on 2018-02-18.

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@@ Line 1: / Line 1: @@
+{{See also|Global descriptor table}}
 In memory addressing for [[Intel]] [[x86]] computer architectures, '''segment descriptors''' are a part of the segmentation unit, used for translating a [[logical address]] to a linear address. Segment descriptors describe the [[memory segment]] referred to in the logical address.<ref>Bovet, D.P., & Cesati, M. (2000). ''Understanding the Linux Kernel (First Edition)''. O'Reilly & Associates, Inc.</ref>
-The segment descriptor (8 bytes long in 80286) contains the following fields:<ref>{{Cite book|first=Daniel|last=Tabak|title=Advanced Microprocessors|publisher=Mcgraw Hill Publishers|page=149|url=https://books.google.com/books?id=i41QAAAAMAAJ|isbn=9780070628434|year=1995}}</ref>
+The segment descriptor (8 bytes long in 80286 and later) contains the following fields:<ref>{{Cite book|first=Daniel|last=Tabak|title=Advanced Microprocessors|publisher=Mcgraw Hill Publishers|page=[https://archive.org/details/advancedmicropro00taba/page/149 149]|url=https://archive.org/details/advancedmicropro00taba|url-access=registration|isbn=9780070628434|year=1995}}</ref>
 # A segment base address
@@ Line 7: / Line 8: @@
 # Control bits
-==x86-64==
+== Structure ==
+The x86 and x86-64 segment descriptor has the following form:<ref>{{Cite tech report|title=AMD64 Architecture Programmer's Manual Volume 2: System Programming|page=80|url=http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/24593_APM_v21.pdf|year=2013|archiveurl=https://web.archive.org/web/20180218024045/http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/24593_APM_v21.pdf|archivedate=2018-02-18}}</ref>
+: [[File:SegmentDescriptor.svg]]
-In [[x86-64]], the code segment descriptor has the following form:<ref>{{Cite techreport|title=AMD64 Architecture Programmer's Manual Volume 2: System Programming|page=80|url=http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/24593_APM_v21.pdf|year=2013}}</ref>
-{| class="wikitable"
-|-
-! 31!!—!!24!!23!!22!!21!!20!!19!!—!!16!!15!!14!!13!!12!!11!!10!!9!!8!!7!!—!!0
-|-
-| colspan="3" | Base Address[31:24]||G||D||L||AVL
-| colspan="3" | Segment Limit[19:16]||P
-| colspan="2" | DPL||1||1||C||R||A
-| colspan="3" | Base Address[23:16]
-|-
-| colspan="10" | Base Address[15:0]
-| colspan="11" | Segment Limit[15:0]
-|}
 Where the fields stand for:
-; Base Address : 32 bit starting memory address of the segment
+; Base Address : Starting memory address of the segment. Its length is 32 bits and it is created from the lower part bits 16 to 31, and the upper part bits 0 to 7, followed by bits 24 to 31.
-; Segment Limit : 20 bit length of the segment. (More specifically, the address of the last accessible data, so the length is one more that the value stored here.)  How exactly this should be interpreted depends on other bits of the segment descriptor.
+; Segment Limit : Its length is 20 bits and is created from the lower part bits 0 to 15 and the upper part bits 16 to 19. It defines the address of the last accessible data. The length is one more than the value stored here. How exactly this should be interpreted depends on the Granularity bit of the segment descriptor.
 ; G=Granularity : If clear, the limit is in units of bytes, with a maximum of 2<sup>20</sup> bytes.  If set, the limit is in units of 4096-byte pages, for a maximum of 2<sup>32</sup> bytes.
+; D/B
-; D=Default operand size : If clear, this is a 16-bit code segment; if set, this is a 32-bit segment
-; L=Long-mode segment : If set, this is a 64-bit segment (and D must be zero), and code in this segment uses the 64-bit instruction encoding
+: D = Default operand size : If clear, this is a 16-bit code segment; if set, this is a 32-bit segment.
+: B = Big: If set, the maximum offset size for a data segment is increased to 32-bit 0xffffffff. Otherwise it's the 16-bit max 0x0000ffff. Essentially the same meaning as "D".
-; AVL=Available : For software use, not used by hardware
+; L=Long : If set, this is a 64-bit segment (and D must be zero), and code in this segment uses the 64-bit instruction encoding. "L" cannot be set at the same time as "D" aka "B". (Bit 21 in the image)
+; AVL=Available : For software use, not used by hardware  (Bit 20 in the image with the label A)
 ; P=Present : If clear, a "segment not present" exception is generated on any reference to this segment
-; DPL=Descriptor privilege level : Privilege level required to access this descriptor
+; DPL=Descriptor privilege level : Privilege level (ring) required to access this descriptor
-; C=Conforming : Code in this segment may be called from less-privileged levels
+; S=System Segment : If clear, this is system segment, if 1, this is Code/Data segment.
+; Type: If bit 11 set, this is a code segment descriptor. If clear, this is a data/stack segment descriptor, which has "D" replaced by "B", "C" replaced by "E" and "R" replaced by "W". This is in fact a special case of the 2-bit type field, where the preceding bit 12 cleared as "0" refers to more internal system descriptors, for LDT, LSS, and gates.
-; R=Readable : If clear, the segment may be executed but not read from
+; C=Conforming : Code in this segment may be called from less-privileged levels.
-; A=Accessed : This bit is set to 1 by hardware when the segment is accessed, and cleared by software
+; E=Expand-Down: If clear, the segment expands from base address up to base+limit. If set, it expands from maximum offset down to limit, a behavior usually used for stacks.
+; R=Readable : If clear, the segment may be executed but not read from.
-Data segments have bit 11 clear, ignore bit 21 (L) and interpret bits 22, 10 and 9 (D, C and R) differently.  Descriptors with bit 12 clear are "system descriptors" and are used for specialized purposes.
+; W=Writable : If clear, the data segment may be read but not written to.
+; A=Accessed : This bit is set to 1 by hardware when the segment is accessed, and cleared by software.
 ==See also==
@@ Line 47: / Line 40: @@
 ==References==
 {{reflist}}
-* {{cite book | last = Tabak | first = Daniel   | title = Advanced Microprocessors | publisher = McGraw Hill and Co.}}
+* {{cite book | last = Tabak | first = Daniel   | title = Advanced Microprocessors | year = 1991 | url = https://archive.org/details/advancedmicropro00dani | url-access = registration | publisher = McGraw Hill and Co.| isbn = 9780070628076 }}
 * {{cite book | last =  Hall | first = Douglas | title = Microprocessors and Interfacing  | publisher = McGraw Hill Publications }}

Segment descriptor: Difference between revisions

Latest revision as of 08:38, 25 July 2023

Structure[edit]

See also[edit]

References[edit]

Further reading[edit]

External links[edit]